Technical Field
This disclosure generally relates to memory devices.
Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory technology. One type of flash memory employs floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer in place of the floating gate.
These types of flash memory cell consist of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a charge storage structure including a tunnel dielectric layer, the charge storage layer (floating gate or dielectric), and a blocking dielectric layer. According to the early charge trapping memory designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunnel dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed of silicon oxide (O), and the gate comprises polysilicon (S). Charge is stored in the charge storage layer by inducing a source-drain current (e.g., by applying a voltage to the gate) that is sufficiently high to move high-energy electrons through the tunnel dielectric layer and trapped in the charge storage structure.
Data is stored in a memory cell of a flash memory device by controlling the amount of charge trapped in the charge storage structure. The amount of charge stored sets a threshold voltage for the memory cell in the flash memory device, which allows the data to be read. Data can be programmed into a flash memory cell by applying voltage pulses to the flash memory cell, causing charge to be stored in the charge storage structure of the flash memory cell. A method for programming a flash memory cell is described in Suh et al., “A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” IEEE International Solid-State Circuits Conference, 1995, page 128-130. According to Suh, in order to program a target memory cell to achieve a threshold within a range representing a particular data value, a sequence of program/verify steps are executed, in which each program pulse in the sequence causes an incremental change in threshold voltage of the cell, and has a magnitude stepped up relative to the previous pulse. Between each pulse in ISPP, a program verify potential is applied to the word line of the cell, and the data is sensed, to determine whether the cell threshold exceeds the program verify level. The program verify level is set at the low end of the range suitable for the target data value. By inducing incremental changes in threshold, a tighter distribution in thresholds above the program verify level can be achieved.
ISPP and other incremental pulse programming schemes can be applied in page program operations, in which memory cells of a page are programmed in parallel. Because the memory cells in the page are likely to have varying responses to program pulses, and may have varying starting threshold levels, some cells will reach the target threshold level in fewer pulses while some cells will require more pulses. For a page program, the sequence continues until all the cells in the page reach their target, and so systems are designed to execute a relatively large number of steps in the programming sequence. Therefore, incremental pulse programming can take a relatively long time. In operations that are designed to program a large number of pages in a row, such as in a one-time program memory device used to store a large data set or computer program, then the time for programming pages is multiplied many times.
It is desirable to provide a method that reduces the programming time for flash memory, including page mode programming times.